The yield in the semiconductor manufacturing front-end process is affected considerably by defects resulting from process abnormalities in various processes for wafer manufacturing and by circuit pattern defects stemming from process fluctuations.
Typically incurred defects include particles randomly produced and attached to the wafer and scratches caused by CMP. Also, there are pattern defects that occur only on the wafer edge as a result of the differences in manufacturing conditions between the wafer center and the waver edge in various processes (e.g., different plasma states in the etch process and differently heated states in the diffusion process).
Also, the representative process fluctuations that incur pattern defects include fluctuations of exposure conditions (in terms of focus and dose) under which circuit patterns are optically exposed in the lithography process. Such fluctuating factors can change the dimensions and shapes of circuit patterns, thereby possibly incurring faulty device properties.
In order to prevent the occurrence of such defects and to realize high-yield manufacturing, defect management and process management at the site of wafer manufacturing are becoming more and more important.
Wafer inspection tools are used for defect management. Traditionally utilized optical wafer inspection tools irradiate the wafer with illuminating light, detect reflected and scattered light from the wafer to image the wafer surface state, and inspect the wafer surface for detects through image processing. As such, the optical wafer inspection tool has throughput of about several to tens of minutes per wafer with detection sensitivity of 20 nanometers or larger. However, under defect detection conditions on the order of tens of nanometers, false alarms (not true defects) are often detected along with actual defects; it is difficult solely to detect true defects with high accuracy.
Meanwhile, SEM (Scanning Electron Microscope) type wafer inspection tools using an electron beam have been known to exist as an apparatus capable of inspection with higher sensitivity than optical wafer inspection tools. This type of apparatus images the state of the wafer surface by irradiating the wafer surface with a focused electron beam about a dozen to tens of nanometers in diameter and by detecting secondary electrons and the like emanating from the wafer surface. Although it has detection sensitivity of a dozen to several nanometers, this apparatus offers drastically lower throughput than optical wafer inspection tools. For this reason, the SEM type wafer inspection tool is often used in partial inspections covering only limited regions over the wafer. Patent Literature 1 and Patent Literature 2 cited below disclose methods for inspecting the wafer in part using an electron beam inspection tool. The disclosed methods involve performing defect inspection by limiting the area for inspection to partial regions such as memory mat peripherals of semiconductor memories.
Incidentally, defect review tools are used to observe and categorize the defects detected by these inspection tools. Since advances in process miniaturization have brought the size of defects affecting yield to smaller than tens of nanometers, electron beam type review tools (review SEM) are generally utilized. Defect position information obtained from the wafer inspection tool is taken as input, and an image of the region of interest is acquired with a resolution higher than at inspection time (e.g., a size of several nanometers per pixel) for identification and observation of types of defects.
Meanwhile, an example of process management is the monitoring of the lithography process using a CDSEM (Critical Dimension-SEM). The CDSEM is used periodically to measure the dimensions of the circuit patterns at predetermined positions on the wafer and to compare the measured dimension values with reference values for process management. Like the above-mentioned review SEM, the CDSEM is an apparatus that uses an electron beam and can acquire images with a resolution of about several nanometers. However, the number of positions that can be measured by this apparatus is limited because it takes as long as seconds to measure one position. For this reason, only predetermined positions are targeted for measurement. Technical Literature 3 cited below discloses a method for identifying the positions required for verification of a tolerable range of process fluctuations and for pattern measurement, using a wafer (e.g., FEM: Focus Exposure Matrix wafer) prepared by changing the exposure conditions for exposure process management into those applicable in units of chips. Incidentally, the FEM wafer is a wafer that has the same circuit pattern formed thereon with the focus and dose of exposure changed in a matrix pattern per die on the wafer. This wafer is subjected to the optical wafer inspection tool for inspection, which makes it possible to determine the location information about the positions where defects actually occurred and the focus and dose conditions that have prevented defects from being formed (the conditions are called the process window). Determined here as the positions to be measured are those that are likely expected to occur during process fluctuations such as defective positions on dies outside the process window.